Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. PLDs can include, for example, re-programmable devices such as Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs), and metal programmable devices such as Application Specific Integrated Circuits (ASICs). PLDs can also be implemented in other ways, e.g., using fuse or anti-fuse technology.
An FPGA typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, block RAM, multipliers, and so forth).
The interconnect structure, CLBs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Some advanced FPGAs include processor blocks embedded in the CLB array. For example, each of the Xilinx Virtex-II Pro™ FPGAs includes several dedicated (fixed-function) processor blocks, each block implementing an IBM® PowerPC® RISC processor. (“IBM” and “PowerPC” are registered trademarks of International Business Machines Corporation.) The Xilinx Virtex-II Pro FPGA is described in detail in pages 19-71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
The presence of dedicated processor blocks in an FPGA has many advantages for a system designer. For example, because of the great flexibility of the programmable resources, they are inherently significantly less area-efficient than dedicated logic. Therefore, a processor implemented in “soft logic” (i.e., using programmable multi-purpose logic blocks and routing) typically consumes a much larger area of the FPGA than a dedicated processor, which is implemented in “hard logic” (i.e., as a block of fixed-function logic).
Pre-designed functional blocks (“cores”) are readily available for implementing processors in FPGAs. A “soft core” is a logic block implemented using multi-purpose programmable resources. An FPGA soft core can be, for example, a predetermined set of configuration bits that program the FPGA to perform one or more functions. A soft core can also be a netlist, source code, or schematics that describe the logic and connectivity of a design. Some soft cores include an optimally floorplanned layout targeted to a specific PLD (e.g., a specific family of FPGAs). Soft cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality. A “hard core” is a block of fixed logic in a PLD that can be incorporated into user designs, such as the dedicated processors in the Virtex-II Pro FPGAs referenced above.
A soft processor core can typically be modified to conform to desired specifications with regard to certain architectural features (e.g., bus widths) and protocols (e.g., bus timing). For example, Xilinx, Inc. offers a soft processor core called the MicroBlaze™ processor, which offers a selectable bit width.
A hard processor core is not as flexible as a soft processor core. A hard processor core possesses a fixed instruction set and operates according to a fixed bus interface protocol. For example, each Virtex-II Pro FPGA includes several IBM PowerPC processor cores. These processor cores support the IBM PowerPC instruction set and the associated bus interface protocol. Because the hard processor cores are implemented in dedicated logic, the instruction set and bus interface protocol of the hard cores cannot be altered.
However, it can be desirable to use a hard processor core to emulate a different processor with a different instruction set and a different bus interface protocol. Common situations in which this emulation is desirable include, for example, the desire to run software developed for a first processor in a system that includes a second and different processor. While a soft processor core could be developed or modified to correspond to the target processor, a hard processor core consumes much less area and can sometimes operate at a faster speed than a corresponding soft processor core. Therefore, it is desirable to provide methods and cores that use a hard processor core already available in a PLD to emulate a different processor with a different instruction set and a different bus interface protocol.
Further, not all PLDs include hard processor cores. However, design resources might not be available to develop a new soft processor core, or to modify an existing soft processor core using presently known methods, to match the instruction set and bus interface protocol of the target processor. Therefore, it is also desirable to provide methods and cores that can easily modify an existing soft processor core to emulate a different processor with a different instruction set and a different bus interface protocol.